1. Field of the Invention
The present invention relates to a semiconductor memory device using a resistive memory element.
2. Description of the Related Art
In recent years, a semiconductor memory utilizing a resistive memory element as a memory element, e.g., an MRAM (Magnetoresistive Random Access Memory), a PCRAM (Phase Change Random Access Memory), or a ReRAM (Resistive Random Access Memory) has attracted much attention.
For example, in an MRAM, a magnetoresistive effect element called an MTJ (Magnetic Tunnel Junction) element is used for a memory element. A magnetoresistive effect element has a structure where an insulating film is sandwiched between two ferromagnetic bodies. A magnetizing direction of one ferromagnetic layer (a magnetization invariable layer) is fixed by an antiferromagnetic layer, and a magnetizing direction of the other ferromagnetic layer (a magnetization free layer) can be freely reversed. Further, a magnetoresistive effect in which a resistance value changes in accordance with a relative magnetizing direction of the magnetization invariable layer and the magnetization free layer in the magnetoresistive effect element is utilized to discriminate data “1” or data “0”.
In recent years, a spin-transfer type MRAM utilizing magnetization reversal based on polarized spin current injection for a write mode has been advanced (see, e.g., U.S. Patent Publication No. 5695864 and 2005 IEDM Technical Digest, pp. 459-462, December 2005). In the spin-transfer scheme, since a current amount required for magnetization reversal (a reversal threshold current) is specified by a current density flowing through a magnetoresistive effect element, reducing an area of the magnetoresistive effect element leads to a decrease in the reverse threshold current. That is, the spin-transfer type MRAM is expected as a technology that can realize a high-capacity semiconductor memory since a reversal threshold current can be scaled. A write operation of the spin-transfer type MRAM is carried out by flowing a write current that is equal to or above a reversal threshold current through the magnetoresistive effect element. A polarity (“0” or “1”) of data is rewritten based on a flowing direction of the write current with respect to the magnetoresistive effect element.
A memory cell used for the MRAM has, e.g., an 1Tr+1MTJ type structure. In this memory cell, one end of a magnetoresistive effect element is connected with a first bit line, the other end of the magnetoresistive effect element is connected with one source/drain of a select transistor, and the other source/drain of the select transistor is connected with a second bit line. Furthermore, a gate of the select transistor is connected with a word line, and many memory cells are connected with one pair of bit lines and a word line, thereby constituting a memory cell array of the MRAM.
An operating speed of the MRAM will now be explained. A switching speed of the magnetoresistive effect element is equal to a magnetization reversal speed of a magnetic body and is very high. For example, in case of a write operation, since a switching speed is dependent on an injection current density in switching of the magnetoresistive effect element based on the spin-transfer scheme, a high-speed operation of approximately 10 ns or less can be usually realized.
However, considering an entire write time including charge/discharge of a write interconnect line (a bit line), since many memory cells are connected with a pair of bit lines, a junction capacitance or the like of a diffusion layer of the select transistor is added to a parasitic capacitance of the interconnect lines.
As a result, an RC time constant of the interconnect lines is in proportion to not only a interconnect length but also the number of memory cells connected with pairs of bit lines. Therefore, the overall write speed in the pair of bit lines cannot be increased beyond a time including an RC product of a write interconnect line.
Therefore, when trying to realize a high-speed write operation, a interconnect length of the write interconnect line must be reduced. However, this means a reduction in scale of the memory cell array, thereby resulting in an increase in chip size and in manufacturing cost.